Core Architecture Overview

The ARM Cortex-M Core

The ARM Cortex-M core implements the ARM architecture, providing the instruction set and execution pipeline. Key features include:

• RISC (Reduced Instruction Set Computing) architecture
• 32-bit processing capability
• Pipeline stages for efficient instruction execution
• Thumb/Thumb-2 instruction sets for code density

Nested Vectored Interrupt Controller (NVIC)

The NVIC manages interrupts with minimal latency and maximum configurability:

• Priority-based interrupt handling
• Nested interrupt support
• Configurable priority levels
• Dedicated SysTick timer for operating system timing

Memory Architecture

Memory Map

The STM32 uses a unified 32-bit address space with memory-mapped peripherals: