Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL)
• Up to 16 I/Os under control • Output states: push-pull or open drain + pull-up/down • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output) • Speed selection for each I/O • Input states: floating, pull-up/down, analog • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input) • Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR • Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration • Analog function • Alternate function input/output selection registers (at most 16 AFs per I/O) • Fast toggle capable of changing every two clock cycles • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral function