• Synchronous and full-duplex communication between a master and several slave devices.
• Uses two pins for data transfer–SDIN and SDO.
• There is a SCLK pin to synchronize data transfer between two chips.
• There is also a CE pin which is used to initiate and terminate the data transfer.

• MOSI: Master Out Slave In, used to send data from master to slave
• MISO: Master In Slave Out, used to send data from slave device to master
• SCK: Serial Clock, used to generate clock to synchronize data transfer between the master and slave device. Generated by master.
• SS: Slave Select, used to select a particular slave in the SPI multiple slaves configuration.

• CPOL = 0 Means sampling on the first edge
• CPOL = 1 Means sampling on the second edge

NSS

• NSS software mode:

  SS line is driven internally by the firmware.

• NSS hardware mode:

  A dedicated GPIO pin is used to drive the SS line.

• NSS Output Enabled:

  Used only when device operates in master mode

• NSS Output Disabled:

  Allows multi-master capability for devices operating in master mode

IT Mode

• NSS hardware mode must be used.
• CPHA and CPOL are forced to conform to Texas Instrument (TI) protocol requirements.